The present invention relates generally to semiconductor devices and the fabrication thereof and, more particularly, to shallow trench isolation (STI) regions for isolating one semiconductor device from another and a method of formation.
Typical semiconductor devices are formed using active regions of a wafer. The active regions are defined by isolations regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an integrated circuit having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on a insulating layer that is, in turn, disposed on a silicon substrate).
As indicated, the active regions of each semiconductor device, MOSFET or otherwise, are often separated by isolation regions. One technique for forming isolation regions is local oxidation of silicon (LOCOS). LOCOS involves depositing a non-oxidizable mask, such as silicon nitride over a thin layer of oxide grown on a blank silicon wafer. The mask is patterned using photolithography and then the wafer is thermally oxidized. Following oxidation, mesa-like regions of silicon are formed that are surrounded by silicon oxide insulation. The active devices are then formed using the silicon mesas. Another technique is deep trench isolation (DTI). DTI has primarily been used for forming isolation regions between bipolar transistors.
Another technique for the formation of isolation regions is shallow trench isolation (STI). STI involves forming trenches in a layer of silicon and then filling the trenches with silicon oxide. Alternatively, the trenches can be lined with a silicon oxide liner formed by a thermal oxidation process and then filled with additional silicon oxide or another material, such as polysilicon. These xe2x80x9cfilledxe2x80x9d trenches define the size and placement of the active regions.
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, (including, for example, MOSFETs, other types of transistors, memory cells, and the like) that are as small as possible. It is also advantageous to reduce the scale of the isolation regions that are formed between the devices. Although the fabrication of smaller devices and isolation regions allows more devices to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. For example, relatively narrow STI regions (e.g., about 180 xc3x85 or less) formed using conventional techniques have a tendency lose their ability to isolate adjacent devices.
Accordingly, there exists a need in the art for improved isolation between semiconductor devices and for techniques of fabricating improved isolation regions along with semiconductor devices.
According to one aspect of the invention, a shallow trench isolation region formed in a layer of semiconductor material is provided. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner.
According to another aspect of the invention, a method of forming a shallow trench isolation region in a layer of semiconductor material is provided. The method includes forming a trench in the layer of semiconductor material, the trench having sidewalls and a bottom; forming a layer of high-K material, the layer of high-K material conforming to the sidewalls and the bottom of the trench to line the trench with a high-K liner; and filling the high-K material lined trench with an isolating material.